Manufacturer
Intel / Altera
Description
CPLD MAX V Family 64 Macro Cells 184.1MHz 1.8V 100-Pin TQFP
Datasheet
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Size
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Nominal Supply Current
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Current
Operating Supply Voltage
Propagation Delay
REACH SVHC
RoHS
Schedule B
Speed Grade
Terminal Pitch
Width
Description
TQFP
Compliant
184.1 MHz
1.2 mm
14 mm
Production (Last Updated: 8 months ago)
152 MHz
85 °C
1.89 V
1 kB
FLASH
0 °C
1.71 V
Surface Mount
25 µA
79
8
80
64
100
79
100
25 µA
1.8 V
7.9 ns
Yes
Compliant
8542390000
4
500 µm
14 mm
MOQ : Unavailable
Minimum Qty : Unavailable
Per Unit Price
Unavailable
Total Price
Unavailable
Ships in 7-10 days from Bengaluru
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Size
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Nominal Supply Current
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Current
Operating Supply Voltage
Propagation Delay
REACH SVHC
RoHS
Schedule B
Speed Grade
Terminal Pitch
Width
Description
TQFP
Compliant
184.1 MHz
1.2 mm
14 mm
Production (Last Updated: 8 months ago)
152 MHz
85 °C
1.89 V
1 kB
FLASH
0 °C
1.71 V
Surface Mount
25 µA
79
8
80
64
100
79
100
25 µA
1.8 V
7.9 ns
Yes
Compliant
8542390000
4
500 µm
14 mm
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