Manufacturer
Intel / Altera
Description
CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 125MHz 5V 44-Pin PLCC Tray
Datasheet
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Speed Grade
Terminal Pitch
Turn-On Delay Time
Width
Description
PLCC
Compliant
166.7 MHz
4.572 mm
Lead Free
16.5862 mm
Obsolete (Last Updated: 8 months ago)
175.4 MHz
85 °C
5.5 V
EEPROM
-40 °C
4.5 V
Surface Mount
1250
36
4
4
64
44
36
44
5 V
7.5 ns
No
Yes
Compliant
8542390000
7
1.27 mm
7.5 ns
16.5862 mm
MOQ : Unavailable
Minimum Qty : Unavailable
Per Unit Price
Unavailable
Total Price
Unavailable
Ships in 7-10 days from Bengaluru
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Speed Grade
Terminal Pitch
Turn-On Delay Time
Width
Description
PLCC
Compliant
166.7 MHz
4.572 mm
Lead Free
16.5862 mm
Obsolete (Last Updated: 8 months ago)
175.4 MHz
85 °C
5.5 V
EEPROM
-40 °C
4.5 V
Surface Mount
1250
36
4
4
64
44
36
44
5 V
7.5 ns
No
Yes
Compliant
8542390000
7
1.27 mm
7.5 ns
16.5862 mm
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