Manufacturer
Intel / Altera
Description
CPLD MAX 7000A Family 2.5K Gates 128 Macro Cells 192.3MHz 3.3V 144-Pin TQFP Tray
Datasheet
Type
Case/Package
China RoHS
Clock Rate
Frequency
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
REACH SVHC
RoHS
Speed Grade
Terminal Pitch
Turn-On Delay Time
Width
Description
TQFP
Compliant
192.3 MHz
192.3 MHz
1.6 mm
Lead Free
20 mm
Obsolete (Last Updated: 8 months ago)
192.3 MHz
70 °C
3.6 V
EEPROM
0 °C
3 V
Surface Mount
2500
100
8
8
128
144
36
144
3.3 V
5 ns
Yes
Compliant
5
500 µm
5 ns
20 mm
MOQ : Unavailable
Minimum Qty : Unavailable
Per Unit Price
Unavailable
Total Price
Unavailable
Ships in 7-10 days from Bengaluru
Type
Case/Package
China RoHS
Clock Rate
Frequency
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Logic Elements/Cells
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
REACH SVHC
RoHS
Speed Grade
Terminal Pitch
Turn-On Delay Time
Width
Description
TQFP
Compliant
192.3 MHz
192.3 MHz
1.6 mm
Lead Free
20 mm
Obsolete (Last Updated: 8 months ago)
192.3 MHz
70 °C
3.6 V
EEPROM
0 °C
3 V
Surface Mount
2500
100
8
8
128
144
36
144
3.3 V
5 ns
Yes
Compliant
5
500 µm
5 ns
20 mm
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