Manufacturer
Lattice Semiconductor
Description
CPLD ispMACH 4A Family 5K Gates 128 Macro Cells 83.3MHz/118MHz 5V 100-Pin PQFP Tray
Datasheet
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Macrocells
Number of Pins
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Terminal Pitch
Turn-On Delay Time
Width
Description
PQFP
Compliant
62.5 MHz
3.4 mm
Lead Free
20 mm
EOL (Last Updated: 7 months ago)
125 MHz
70 °C
5.25 V
EEPROM
0 °C
4.75 V
Surface Mount
5000
64
264
128
100
100
5 V
10 ns
No
Yes
Compliant
8542390000, 8542390000|8542390000|8542390000|8542390000|8542390000
650 µm
10 ns
14 mm
MOQ : Unavailable
Per Unit Price
₹Infinity
Total Price
₹Infinity
Ships in 7-10 days from Bengaluru
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Lead Free
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Logic Blocks (LABs)
Number of Macrocells
Number of Pins
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Terminal Pitch
Turn-On Delay Time
Width
Description
PQFP
Compliant
62.5 MHz
3.4 mm
Lead Free
20 mm
EOL (Last Updated: 7 months ago)
125 MHz
70 °C
5.25 V
EEPROM
0 °C
4.75 V
Surface Mount
5000
64
264
128
100
100
5 V
10 ns
No
Yes
Compliant
8542390000, 8542390000|8542390000|8542390000|8542390000|8542390000
650 µm
10 ns
14 mm
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