Manufacturer
Lattice Semiconductor
Description
CPLD MACH 5 Family 10K Gates 256 Macro Cells 83.3MHz/125MHz 3.3V 100-Pin PQFP Tray
Datasheet
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Terminal Pitch
Width
Description
PQFP
Non-Compliant
71 MHz, 100 MHz
3.4 mm
20 mm
Obsolete (Last Updated: 8 months ago)
100 MHz
70 °C
3.6 V
EEPROM
0 °C
3 V
Surface Mount
10000
68
256
100
208
100
3.3 V
7.5 ns
No
No
Non-Compliant
8542390000, 8542390000|8542390000|8542390000|8542390000|8542390000
635 µm
14 mm
MOQ : Unavailable
Minimum Qty : Unavailable
Per Unit Price
Unavailable
Total Price
Unavailable
Ships in 7-10 days from Bengaluru
Type
Case/Package
China RoHS
Clock Rate
Height - Seated (Max)
Length
Lifecycle Status
Max Frequency
Max Operating Temperature
Max Supply Voltage
Memory Type
Min Operating Temperature
Min Supply Voltage
Mount
Number of Gates
Number of I/Os
Number of Macrocells
Number of Pins
Number of Programmable I/O
Number of Terminals
Operating Supply Voltage
Propagation Delay
Radiation Hardening
REACH SVHC
RoHS
Schedule B
Terminal Pitch
Width
Description
PQFP
Non-Compliant
71 MHz, 100 MHz
3.4 mm
20 mm
Obsolete (Last Updated: 8 months ago)
100 MHz
70 °C
3.6 V
EEPROM
0 °C
3 V
Surface Mount
10000
68
256
100
208
100
3.3 V
7.5 ns
No
No
Non-Compliant
8542390000, 8542390000|8542390000|8542390000|8542390000|8542390000
635 µm
14 mm
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